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Common design guidelines
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All signals are simulated load capacitance at 15pF@200MHz, 1.8V. So, all capacitance including the
board parasitic must be smaller than 15pF.
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Line impedance 45 ~ 55 ohm.
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Minimize the branch length.
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Maximum the length: under 45mm.
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Signal nets should be referenced with Ground & Power plane.
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Route most segments in inner layer.
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Power signal must be reinforced as soon as possible. Also, the bypass capacitors have to be
located closely to the power pads.
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Place 2 more decoupling capacitors for power net per a DRAM.
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Use solid Power & Ground plane for DRAM signal reference.
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Design guidelines for Xm1DQS and Xm1DATA, Xm1DQM net
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Xm1DQS0 & Xm1DATA[7:0], Xm1DQM0 Skew: -/+ 50ps (Target length: -/+ 5.0mm)
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Xm1DQS1 & Xm1DATA[15:8], Xm1DQM0 Skew: -/+ 50ps (Target length: -/+ 5.0mm)
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Xm1DQS2 & Xm1DATA[23:16], Xm1DQM0 Skew: -/+ 50ps (Target length: -/+ 5.0mm)
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Xm1DQS3 & Xm1DATA[31:24], Xm1DQM0 Skew: -/+ 50ps (Target length: -/+ 5.0mm)
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Xm1DQS0 & Xm1DQSn0 Skew: -/+ 10ps (Target length: -/+ 1.0mm) for DDR2
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Xm1DQS1 & Xm1DQSn1 Skew: -/+ 10ps (Target length: -/+ 1.0mm) for DDR2
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Xm1DQS2 & Xm1DQSn2 Skew: -/+ 10ps (Target length: -/+ 1.0mm) for DDR2
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Xm1DQS3 & Xm1DQSn3 Skew: -/+ 10ps (Target length: -/+ 1.0mm) for DDR2
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Design guidelines for Xm1SCLK and Xm1SCLKn
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Star topology is recommenced.
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Recommended differential impedance is 100 ohm.
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Xm1SCLK & Xm1SCLKn Skew: -/+ 10ps (Target length: -/+ 1.0mm).
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Xm1SCLK(n) & Xm1DQS[3:0] Skew: -/+ 100ps (Target length: -/+ 10mm).
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Design guidelines for control signals
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Xm1SCLK(n) & Xm1ADDR[15:0], Xm1CASn, Xm1RASn, Xm1CKE[1:0], Xm1WEn Skew: -/+ 100ps

(Target length: -/+ 10mm).
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T-branch topology is recommenced for Command, Address and Control net.
(Xm1CKE[1:0], Xm1CSn[1:0], Xm1ADDR[15:0], Xm1RASn, Xm1CASn, Xm1WEn)
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Do not route near high speed signals (Xm1SCLK, Xm1SCLKn, Xm1DQS(n)[3:0] and Xm1DATA net)
or have enough spacing over 3*WIDTH.
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Direct connect Xm1GATEI (pin B10) to Xm1GATEO (pin C10).
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Pattern Length guidelines
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According to line impedance and drive strength, pattern length is put in the range of value described
as below.
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This value is available in the case of using DDR @ ~133MHz. (VDD and VDDQ=2.5V)
4.7 HDMI
The bandwidth of TMDS/LVDS transmission can over 1.6GHz. The impedance matching problem must be taken
care. The characteristic impedance of the differential signal pair should be 50 . each, which is controlled by the
width and space of the differential signal pair.
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Minimum 4-Layer PCB with internal power/ground should be used
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TX2P/N, TX1P/N, TX0P/N, TXCP/N line should have differential 100 impedance
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To reduce coupling between high-speed data lines, each differential pair should have enough
distance to other differential pairs
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The differential pairs should be routed as pairs as shortly as possible and hence each length is
matched (Maximum Length : 1.2inch)
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Differential lines should be placed far away from CMOS clock and data lines (Oscilatorˇs In/Out,
Drive Strength05101520253035404570ohm60ohm50ohm40ohm30ohmLine ImpedanceZoPattern Length (mm)
10mA5mA

DRAM Clock/Data etc.)
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Generally, to achieve the characteristic impedance mentioned above, the line width of each of the
differential signal pair is about 8 mils and the space between them is 10mil when the height between
the copper layer and the GND plane is 6mil (in 4 layer PCB board).
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Use 27MHz clock source(X27mXTI, X27mXTO) with 10ppm X-tal(Oscilator)
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Itˇs important Power quality. Use bypass & bulk Capacitors correctly.
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Special bypassing is recommended for the high speed power supply pins due to their sensitivity to
power supply noise coupling. These power pins supply internal analog and clock generation blocks
and are sensitive to power supply noise. Attention should be paid to proper isolation and bypassing
of these pins.
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All bypass capacitors should be connected to the power and ground plane with a low inductance
connection
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The bulk bypass capacitor(s) should have good high frequency characteristics. A capacitor with low
ESR (Equivalent Series Resistance) should be used. It should be located close to the source of the
power(output pin of regulator or connector pin for off board regulators).
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Local high frequency bypass should also be implemented. Capacitors should be located on all four
sides of the chip close to the VDD/VSS pins. The following capacitor is recommended for local
bypass:
Ceramic X7R Dielectric - 0.01uF
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For a slight improvement in high frequency impedance of the bypass capacitors, two capacitors in
parallel can be used for local bypass. The paired capacitors must be located as close as possible to
each other. The following values are recommended for the capacitor pairs:
Ceramic X7R Dielectric - 0.1uF,Ceramic X7R Dielectric - 1nF
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For the ferrite beads (L1, L2, L3), the parasitic resistance value should be small enough such
as 0.001ohm. If this resistance is large, there would be an IR drop in the board.

4.8 Characteristic Impedance
4.8.1 DRAM Memory
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Memory : 100. ∮ 5%(Differential), single 50. ∮ 10% ,