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ATMEL A5D31 SDRAM Layout Guide

Placement：

Placement:

1. 電源電容須放在對應的PAD下方

1 power supply capacitor shall be placed under the corresponding PAD

Trace：

Trace:

1. 同組訊號線須走同一層

The group with 1 signal lines must walk the same layer

a. Group1(第一層)：

A. Group1 (the first layer):

Net Name：DDR_DQM0、DDR_DQS0、DDR_D0~DDR_D7

Net Name:DDR_DQM0, DDR_DQS0, DDR_D0~DDR_D7

b. Group2(第一層)：

B. Group2 (the first layer):

Net Name：DDR_DQM1、DDR_DQS1、DDR_D8~DDR_D15

Net Name:DDR_DQM1, DDR_DQS1, DDR_D8~DDR_D15

c. Group3(第三層)：

C. (third): Group3

Net Name：DDR_DQM2、DDR_DQS2、DDR_D16~DDR_D23

Net Name:DDR_DQM2, DDR_DQS2, DDR_D16~DDR_D23

d. Group4(第三層)：

D. Group4 (the third layer):

Net Name：DDR_DQM3、DDR_DQS3、DDR_D24~DDR_D31

Net Name:DDR_DQM3, DDR_DQS3, DDR_D24~DDR_D31

e. Group6(第三層)：Net Name： DDR_CLK、DDR_CLKN

E. Group6 (third):Net Name: DDR_CLK, DDR_CLKN

*L4對應到L3 CLOCK的區(qū)塊禁止走線，請用GND Plane包覆

*L4 corresponds to the L3 CLOCK blocks forbidden line, please coated with GND Plane

f. Group5(第六層)：

F. (sixth): Group5

Net Name：DDR_CAS、DDR_RAS、DDR_WE、DDR_CKE、DDR_CS

Net Name:DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE, DDR_CS

g. Group6(第一層)：DDR_VREF

G. Group6 (the first layer):DDR_VREF

*和其它訊號線、電源或地線間距150 mil

* and other signal lines, power supply or ground distance of 150 mil

2. 線長：

The 2 line:

a. 全部訊號線長度需小于2000 mil或更短

All A. signal line length must be less than 2000 mil or less

b. Clock線長最短與最長誤差10mil

B. Clock the length of the shortest and longest error 10mil

c. 全部訊號線(CLOCK、DQS、DQM、DQ、Address、Command)

C. all signal lines (CLOCK, DQS, DQM, DQ, Address, Command)

須等長，線長最短與最長誤差10mil

To be equal, the length of the shortest and longest error 10mil

3. 線寬、線距：

The 3 line width, line spacing:

a. 阻抗表：

The A. impedance chart:

6層板 1.2T

6 laminates 1.2T

層別 單端阻抗值及對應之層別與線寬 差動阻抗值及對應之層別與線寬/線距

Layer don't single end impedance value and the corresponding layer don't and linewidth differential impedance value and the corresponding layer don't and line / space

50 90 100

5090100

L1 5.5 5.5/6 4.5/6

L1 5.5 5.5/6 4.5/6

L3 6 5/6 4/7

L3 6 5/6 4/7

L4 6 5/6 4/7

L4 6 5/6 4/7

L6 5.5 5.5/6 4.5/6

L6 5.5 5.5/6 4.5/6

b. 同Group單線間距：12mil

B. with Group single line spacing: 12mil

c. 不同Group間距：20 mil

C. Group: 20 mil with different spacing

d. DDR_VREF 線寬：10 ml

D. DDR_VREF line width: 10 ml

4. 全部訊號線請使用圓弧繞線、不可使用45度繞線

4 of all signal lines, please use the circular arc winding, do not use 45 degrees around the line

5. 由TOP至其它層的Via請全部靠近CPU及SDRAM

5 from TOP to other layers of the Via please close to CPU and SDRAM

6. 上下層的訊號線盡可能不要平行、要90度交叉

The 6 signal line layer as far as possible, not parallel to the 90 degree cross

Plane：

Plane:

Net Name：VDDIODDR 請在L5 VCC層鋪整片

Net Name:VDDIODDR please spread the tablets in L5 VCC layer

Net Name：1V8請走L5 VCC，線寬需40 mil

Net Name:1V8 go L5 VCC, width 40 mil