IMAX6SL高性能處理器的pcb設計。
以下是Ddr Ram 設計的時候需要注意的地方,現以4層板設計為案例說明,阻抗,DRAM注意事項,Dram等長關系(ADDR,DATA,CLK)
1. Impendence matching
90 ohm = W:5 S:6
100 ohm = W:4 S:7
50 ohm = W:5
|
2 Clock 訊號線需要以 Top 為主
如果從 CPU 需要灌孔出來就已 Bottom 層為主,Clock 灌孔處需打 2 點 GND Via
DRAM Address/Data: 50 Ohm,最多Via 兩個
Clock line 請使用弧線走
3 DRam
Signals | Length | Considerations |
Address and bank | Clock length | Match the signals ± 25 mils of the value specified in the length column |
Data and buffer | Clock length | |
Control signals | Clock length | |
Clock | Lcritical (3 inches) | Match the signals of clocks signals ± 5 mils. |
DQS and DQS_B | Clock length | Match the signals of DQS signals ± 10 mils of the value specified in the length column. |