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1.1. PCB Layout Rules
1.1.1. Power input is 48V 4A therefore Power input trace is 160mil.
1.1.2. Compared with normal digital trace, the clock and other high speed signal traces should be short and wide apart as possible. It is better to have a full ground plane under these traces, and if possible, with GND plane around.
1.1.3.  Differential trace .
1. S17C_SIP Differential trace impedance is 100ohm.
2. Route differential pairs close together and away from everything else.
3. Keep both traces of each differential pair lengths as equal as possible.
4. Avoid crossing each pair with neighboring pairs between the chip and magnetic space.
5. Maintain the transmit and receiving separation by placing all the transmit termination
components on one side of the board and all the receiving components on the other side.
      6. P?_TRX?+ and P?_TRX?- are Differential pair. 
      7. S17C_SIP, S17C_SIN and S17C_SOP, S17C_SON are Differential trace.

1.1.4. Single-ended trace impedance target is 50ohm.

1.1.5.  Crystal Circuit(X1)
 Top/GND/Bottom Layer for QCA8337:Run XˇTAL ground planes as solid square on Top/GND/Bottom layer. For isolation purpose place a 20~40mil moat around the XˇTAL ground plane to separate XˇTAL ground from signal ground.
 Vcc layer:Vcc layer region within XˇTAL plane should be dug out and keep clear.


Crystal GND (Bottom Layer)

1.1.6. The relationship of FGND and GND
 Use FGND to shield the RJ45 and transformer region ,except high pot isolation region
 The distance between FGND and GND:A=80~120mil
 The distance between FGND and high pot isolation region:B=75mil

1.1.7.  3.3V_SWR and LX signal
 LX trace doesnˇt change to any layer and keep it at top-layer.
 Lx trace length is as short as possible and a large area. The 1.2V output side needs also a large copper area.
 Some important trace, power and components donˇt close or route to LX trace in particular all 3.3V power and P1ˇs twist-pair.
 VDD33_SWR trace width must be over 15mil. The via / trace of VDD33_SWR can't be closed to LX trace.

1.1.8. TPS54260-Q1 Power Switching Chip
1. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure TPS54260-Q1 PCB Layout Example for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad.
2.The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC.
3.The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load.
4. The top side ground area must provide adequate heat dissipating area.
5. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace.
6. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts,

1.1.9. PoE TPS23851 Layout
1. C69 need close to U7.16 and U7.15.
2. PC84,PD19,PR30,PQ9,PC85 need close to U7.16.
3. PQ1~PQ4 need place on bottom for eliminate heat.
4. C71 need close to U7.28 and U7.21
5.  A proper, high-performance layout relies on grouping the current sense resistors of all 4 ports in a cluster, close to the TPS23851 such that the -48-V return of these resistors forms a star connection. At the central point of that star, is the one and only connection point for the VEE pin of the TPS23851. The VEE power feed also braches off from that same star point to the supply. The four SENx pins should terminate right at the top side of each 0.5- resistor with a separate path from that same end to the source of the
corresponding power FET.
6. The figure below shows the Kelvin connection for the SENx trace to the sense resistors.

7. SENx R(PR15~18),OUT R(PR13, PR23, PR33, PR43),GATE R(PR14, PR24, PR34, PR44).
8.  (PC11, PC21, PC31, PC41 and PD12, PD22, PD32, PD42 are port related components to protect against external voltage surges, reduce EMI and absorb ESD strikes to the port. It is preferable to locate these components closer to the corresponding port and port magnetics.
9.  PD13, PR12, and PC13 should be clustered together whereas PD14 should be located in the high current path and close to the drain of PQ1
10. Power MOSFET
      Careful thermal design should be considered for power MOSFET Q1.1. The power drain tab of this SOT223 should be soldered directly to a copper heat spreader under the device. The area of that heat spreader should be maximized. The spreader should be augmented with additional connections to thermal heat spreaders in the core of the circuit board or on the backside. The combined area of the heat spreaders should be at least 0.5 inches, but this is very dependent on the thermal characteristics of the specific application. Traces in the high current paths of the drain and source nodes should be at least 15-mils wide, leading to the magnetics and port RJ45 connectors.